Integer Representation of Floating-Point Manipulation with Float Twice



How to Cite

Kurniawan, W., Ardiansyah, H., Oktavianita, A. D., & Tahe, M. F. (2020). Integer Representation of Floating-Point Manipulation with Float Twice. IJID (International Journal on Informatics for Development), 9(1), 15–20.


In the programming world, understanding floating point is not easy, especially if there are floating point and bit-level interactions. Although there are currently many libraries to simplify the computation process, still many programmers today who do not really understand how the floating point manipulation process. Therefore, this paper aims to provide insight into how to manipulate IEEE-754 32-bit floating point with different representation of results, which are integers and code rules of float twice.  The method used is a literature review, adopting a float-twice prototype using C programming. The results of this study are applications that can be used to represent integers of floating-point manipulation by adopting a float-twice prototype. Using the application programmers make it easy for programmers to determine the type of program data to be developed, especially those running on 32 bits floating point (Single Precision).


R. E. Bryant and D. R. O. Hallaron, Computer Systems. A Programmer’s Perspective [3rd ed.]. Boston: Pearson, 2016.

M. Drumond, T. Lin, B. Falsafi, and M. Jaggi, “Training Dnns with hybrid block floating point,” Adv. Neural Inf. Process. Syst., vol. 2018-Decem, no. NeurIPS, pp. 453–463, 2018.

S. Janakiraman, K. Thenmozhi, J. B. B. Rayappan, and R. Amirtharajan, “Lightweight chaotic image encryption algorithm for real-time embedded system: Implementation and analysis on 32-bit microcontroller,” Microprocess. Microsyst., vol. 56, pp. 1–12, 2018.

Y. P. You, T. C. Lin, and W. Yang, “Translating AArch64 floating-point instruction set to the x86-64 platform,” ACM Int. Conf. Proceeding Ser., 2019.

X. Lian, Z. Liu, Z. Song, J. Dai, W. Zhou, and X. Ji, “High-performance fpga-based cnn accelerator with block-floating-point arithmetic,” IEEE Trans. Very Large Scale Integr. Syst., vol. 27, no. 8, pp. 1874–1885, 2019.

U. Sidi, M. Ben Abdellah, M. Fez, D. Chenouni, M. Berrada, and A. Tahiri, “Paper—A Serious Game for Learning C Programming Language Concepts Using Solo Taxonomy A Serious Game for Learning C Programming Language Concepts Using Solo Taxonomy Alaeeddine Yassine,” iJET, pp. 110–127, 2017.

A. Sanchez-Stern, P. Panchekha, S. Lerner, and Z. Tatlock, “Finding root causes of floating point error,” ACM SIGPLAN Not., vol. 53, no. 4, pp. 256–269, 2018.

C. Series, “Analysis and Research of Sorting Algorithm in Data Structure Based on Analysis and Research of Sorting Algorithm in Data Structure Based on C Language,” 2020.

S. Smith, Programming with 64-Bit ARM Assembly Language. Canada: Apress, 2020.

K. D. Rao, P. V. Muralikrishna, and C. Gangadhar, “FPGA Implementation of 32 Bit Complex Floating Point Multiplier Using Vedic Real Multipliers with Minimum Path Delay,” 2018 5th IEEE Uttar Pradesh Sect. Int. Conf. Electr. Electron. Comput. Eng. UPCON 2018, pp. 1–6, 2018.

J. J. J. Nesam and S. Sivanantham, “An area-efficient 32-bit floating point multiplier using hybrid GPPs addition,” 2017 Int. Conf. Microelectron. Devices, Circuits Syst. ICMDCS 2017, vol. 2017-Janua, pp. 1–4, 2017.

A. Burud and P. Bhaskar, “Design and Implementation of FPGA Based 32 Bit Floating Point Processor for DSP Application,” Proc. - 2018 4th Int. Conf. Comput. Commun. Control Autom. ICCUBEA 2018, no. ref 15, pp. 1–5, 2018.

P. Lindstrom, S. Lloyd, and J. Hittinger, “Universal coding of the reals: Alternatives to IEEE floating point,” ACM Int. Conf. Proceeding Ser., no. March, 2018.

I. Corporation, “[3]Intel ® 64 and IA-32 Architectures Software Developer ’ s Manual Documentation Changes,” System, vol. 3, no. 253665, 2011.

C. R. S. Hanuman and J. Kamala, “Hardware Implementation of 24-bit Vedic Multiplier in 32-bit Floating-Point Divider,” 2018 4th Int. Conf. Electr. Electron. Syst. Eng. ICEESE 2018, pp. 60–64, 2018.

A. M. San and A. N. Yakunin, “Hardware implementation of floating-point operating devices by using IEEE-754 binary arithmetic standard,” Proc. 2019 IEEE Conf. Russ. Young Res. Electr. Electron. Eng. ElConRus 2019, pp. 1624–1630, 2019.

R. Watpade and P. Palsodkar, “BSD adder for floating point arithmetic: A review,” Proc. 2017 IEEE Int. Conf. Commun. Signal Process. ICCSP 2017, vol. 2018-Janua, pp. 553–556, 2018.

L. Kamble, P. Palsodkar, and P. Palsodkar, “Research trends in development of floating point computer arithmetic,” Proc. 2017 IEEE Int. Conf. Commun. Signal Process. ICCSP 2017, vol. 2018-Janua, no. April, pp. 329–333, 2018.

C. R. Semiawan, Metode Penelitian Kualitatif: Jenis, Karakteristik dan Keunggulannya. Jakarta: Grasindo, 2010.

S. A. Bawankar and P. G. D. Korde, “Review on 32 bit single precision Floating point unit ( FPU ) Based on IEEE 754 Standard using VHDL,” Int. Res. J. Eng. Technol., vol. 4, no. 2, pp. 1077–1082, 2017.

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